This application claims the priority benefit of Taiwan application serial no. 90110253, filed on Apr. 30, 2001.
1. Field of Invention
The present invention relates to a method of manufacturing a thin film transistor and associated driving device. More particularly, the present invention relates to a method of manufacturing a thin film transistor and associated driving device by forming a photoresist layer having a base section and a top section. The top section patterns out thin film transistor""s gate while the base section patterns out a lightly doped drain (LDD) or undoped region so that one less masking step is required.
2. Description of Related Art
Thin film transistors (TFTs) are now frequently used inside liquid crystal displays (LCD) and related products. In general, thin film transistors can be classified according to material types into two major groups, amorphous silicon thin film transistors and polysilicon thin film transistors. Although the amorphous thin film transistor generally has a lower leakage current, low field effect mobility often leads to a lower overall conductive current. On the other hand, although the polysilicon thin film transistor has a higher field-effect mobility and is able to produce a higher conductive current, leakage current is high, resulting in a small current on/off ratio (Ion/Ioff) Hence, widespread application of polysilicon thin film transistors in wide area liquid crystal displays is difficult. To reduce leakage current in a thin film transistor, lightly doped drain structures are often formed on each side of the transistor gate
FIGS. 1A through 1C are schematic cross-sectional views showing the steps for producing a conventional thin film transistor with lightly doped drain regions. First, as shown in FIG. 1A, an insulating substrate 100 is provided. A polysilicon layer 102, a gate oxide layer 104 and a gate layer 106a are sequentially formed over the insulating substrate 100. A patterned photoresist layer 108 is formed over the gate layer 106a. 
As shown in FIG. 1B, the gate layer 106a is etched using the patterned photoresist layer 108 as a mask to form a gate electrode 106b. Thereafter, using the patterned photoresist layer 108 again as a mask, a light implantation 116 is carried out implanting n-type ions into the polysilicon layer 102 to form a lightly doped n-type region 110. The patterned photoresist layer 108 is removed.
As shown in FIG. 1C, another patterned photoresist layer 112 is formed over the gate electrode 106b and the lightly doped n-type regions 110 on each side. Using the patterned photoresist layer 112 as a mask, a heavy implantation 118 is conducted, implanting n-type ions into the lightly doped n-type regions 110 to form a heavily doped n-type region 114 on each side of the gate 106b. The photoresist-covered lightly doped regions 110 form lightly doped drain (LDD) regions 110a. The pair of heavily doped n-type regions 114 serves as a source and a drain terminal of the transistor. Because the lightly doped regions 110a are formed using the patterned photoresist layer 112 as a mask, the width of the lightly doped region 110a may vary according to the alignment accuracy of the photoresist layer 112. Hence, an unsymmetrical source/drain terminal may be produced.
FIGS. 2A through 2C are schematic cross-sectional views showing the steps for fabricating a conventional thin film transistor with lightly doped structures and its associated driver The process includes forming a pixel thin film transistor (TFT) and a complementary metal-oxide-semiconductor (CMOS) transistor on a substrate, with the CMOS transistor serving as a driving device for the TFT.
As shown in FIG. 2A, an insulating substrate 200 is provided. The insulating substrate 200 includes a p-type thin film transistor region 200a, an n-type thin film transistor region 200b and a pixel thin film transistor region 200c. An oxide layer 201, a patterned polysilicon layer 202, a gate oxide layer 204 and a gate layer 206 are sequentially formed over the insulating substrate 200. A patterned photoresist layer 208 is formed over the gate layer 206. The gate layer 206 is etched to form a gate electrode 206a for the p-type thin film transistor, a gate electrode 206b for the n-type thin film transistor and a gate electrode 206c for the pixel thin film transistor. Thereafter, again using the patterned photoresist layer 208 as a mask, a light implantation 216 is conducted, implanting n-type ions into the polysilicon layer 202 to form lightly doped n-type regions 210. The patterned photoresist layer 208 is finally removed.
As shown in FIG. 2B, another patterned photoresist layer 212 is formed over the p-type thin film transistor region 200a, the pixel thin film transistor gate 206c and the lightly doped n-type region 210 on each side of the gate 206c. A heavy implantation 218 is conducted implanting n-type ions into the exposed lightly doped n-type regions 210 to form heavily doped n-type regions 214.
As shown in FIG. 2C, yet another patterned photoresist layer 213 is formed over the n-type thin film transistor region 200b and the pixel thin film transistor region 200c A heavy implantation 220 is conducted implanting p-type ions into the exposed lightly doped n-type region 210 to form heavily doped p-type regions 222.
In a conventional single thin film transistor or array production, at least two photo masks are required. One photomask is used for patterning out various gate electrodes and forming various lightly doped regions through a light implantation. A second photomask is formed over the gate electrodes (the pixel thin film transistor gate) and the sides of the gate electrodes for patterning out the lightly doped drain regions. Since the lightly doped drain regions and the gate electrodes are not formed by a self-aligned process, any misalignment between the two masks may produce non-symmetrical source and drain terminals. Any non-symmetry in the lightly doped drains and the source/drain terminals is a major factor affecting the performance of the pixel thin film transistor.
In addition, quality of the array of thin film transistors on a substrate may vary in accordance with the alignment accuracy of each batch or block. Hence, exposure and alignment accuracy of both masking processes is critical to the ultimate quality of the thin film transistors.
Accordingly, one object of the present invention is to provide a method of forming a thin film transistor and associated driver by forming a photoresist layer having a base section and a top section. The top section patterns out thin film transistor""s gate while the base section patterns out a lightly doped drain (LDD) or undoped region. Ultimately, one less masking step is required and both the lightly doped drain region and the gate electrode are self-aligned.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a thin film transistor. First, a substrate is provided. A patterned polysilicon layer, a gate oxide layer and a gate layer are sequentially formed over the substrate. A photoresist layer is formed over the gate layer. The photoresist layer includes a base section and a top section with width of the base section greater than width of the top section. A portion of the gate layer is removed to expose the gate oxide layer using the photoresist layer as a mask An ion implantation is carried out using the photoresist layer as a mask to form a first doped region. A pre-defined thickness is removed from the photoresist layer so that photoresist material outside the top section is completely removed, exposing the gate layer underneath. Finally, the exposed gate layer is removed to form a gate electrode. The aforementioned process saves a masking step and both the lightly doped region and the gate electrode are self-aligned. Since subsequent processing steps are identical to a conventional method, detailed description is omitted here.
This invention also provides a method of forming a thin film transistor and associated driver. The aforementioned method of forming a thin film transistor is applied to form a pixel thin film transistor over the substrate. Thereafter, a complementary metal-oxide-semiconductor (CMOS) driver is fabricated. The order of forming the pixel thin film transistor and the CMOS driver depends on actual processing requirements. The pixel thin film transistor may be fabricated before the CMOS driver or vice versa. In the fabrication of an array of pixel thin film transistors, one masking step is saved. Moreover, both the lightly doped regions and the gate electrodes are formed by a self-aligned process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.